Career Objective
Bridge the gap between students and knowledge as a teaching professional; and continues involvement of myself in the research activity with full courage and joy for the development of individual and society.
Ph.D.
Specialization in Micro and Nano Electronics under the Electronics and Communication Engineering department from Indian Institute of Information Technology, Design and Manufacturing (IIITDM), Jabalpur (M.P.), with 8.5 CGPA, from January 2016 to January 2019
Thesis Title: Electrically Doped Tunnel Field Effect Transistor with New Design Approaches: Proposal and Investigation
Published total 28 SCI papers; 9 papers as a first author and 19 as a co-author in various reputed international journals such as IEEE, Springer, Elsevier and IOP Sciences
Published 2 papers in renowned international conferences and 4 book chapters with eminent publishers
Research Interest
Modeling and simulation of micro nano semiconductor devices.
Design of nano device sensors for biomedical applications.
Linearity and high frequency analysis of hetero-material devices.
Modeling and simulation of negative capacitance in ferroelectric thin films.
Tool : Silvaco, Sentaurus, SPICE and MATLAB
Work Experience
Currently working as an Assistant Professor at Sardar Vallabhbhai National Institute of Technology, Surat, Gujarat, from 16th April 2021 - till date
Worked as an Assistant Professor at RGM College of Engineering and Technology, Nandyal, Kurnool, A.P., from 17th June 2019 – 10th April 2021
Worked as teaching assistant (research scholar) at IIITDM Jabalpur M.P., from January 2016 - April 2019
Awards and Achievements
MHRD, GOI, sponsored scholarship for Ph.D. program
Active reviewer of various reputed SCI journals and conferences like IEEE, Elsevier, Springer, Taylor & Francis and Scopus
Presented research papers and participated in international conferences such as IEEE ICEE and IEEE-INDICON
Participated in “INUP workshop on nanofabrication technologies” at IIT Bombay from 27 to 30 December 2016
Participated in IEP program on “Design issues related to deep submicron technologies” at VNIT Nagpur from 5 to 9 December 2016
GATE qualified
Scored third position in the state level essay competition while schooling
Received “MEDHAVI CHATRA” award from M.P. government
Personal Details
Date of birth: 13 July, 1987
Father's Name: Indramani Yadav
Marital Status: Married
Current Address: 12A, Flat no. 202, Green city, Pal bhatha, near baghban circle, Surat, Gujarat, pin-395009